A semiconductor package is used to house an integrated circuit (IC) chip to protect it and provide it with electrical connectors for attachment to an printed circuit (PC) board. As shown in FIG. 1, the IC chip or die 11 is positioned on top of a die attachment pad (DAP) 12 which is housed in a package 13, typically made of plastic. The die 11 is electrically connected to an PC board (not shown) by wires 14 which are connected to leads 16. The die 11 is attached to the DAP 12 by adhesive material 17 such as epoxy or soft solder.
During board assembly of electronic or computer products, each lead and IC board electrical connection is individually soldered. However, in surface mount technology, the IC chips' and board's electrical connections are formed by baking the entire unit in an oven at a temperature of approximately 230.degree. C. The unit is then cooled to room temperature. The screening tests for military applications includes temperature extremes from -60.degree. C. to 150.degree. C. An electrically conductive adhesive material bonds the leads of the semiconductor package to the board. Surface mount technology provides a finished product of greatly reduced size and requires significantly less labor in its manufacture than one produced by conventional technology.
During processing the board and packaged IC chips, are therefore subjected to temperature extremes totalling approximately 230.degree. C. These temperatures subject the IC chip contents of the semiconductor package to thermal stress which can damage and reduce the structural integrity of the IC chip.
The following table lists the coefficients of thermal expansion of the components of a semiconductor package.
______________________________________ Selected Packaging Materials Properties Coefficient of Thermal Expansion Material CTE (.times.10.sup.-6 /.degree. C.) k (W/m. .degree. K.) E (.times.10.sup.6 psi) ______________________________________ Plastic Package 30-85 0.837 2.2 i.e., Molding Compound (B-8) Silicon 2.8-3.6 84 10.6 Copper 18 398 18 ______________________________________
It is evident therefrom, that there is substantial mismatch of thermal coefficients with respect to neighboring components. For example, the coefficient of thermal expansion of silicon of the die 11 is at least ten time higher than that of and the plastic molding compound of the package 13, such being a poor thermal conductor. The result of the mismatch is that the heat in the die 11 does not flow freely from the die 11 through a thick mold compound and therefore thermal stress is induced on the die 11.
Thermal stress on die 11 can cause varying levels of damage to the die. Because the die's ends 18 are subject to a much higher thermal stress during the heating and cooling stages of the package mounting on or demounting from the PC board, the die bends as shown in FIGS. 2A, 2B and 2C. The die also experiences high thermal stress when the device/package is going through thermal cycling continuously from peak loading to normal loading or from power-down to power-up during actual device/package life operating conditions. During the heating, the die tends to expand, however, this expansion is prohibited because of the mold compound and therefore, the thermal stress builds up. FIG. 2A represents the die's bending during the heating stage of processing. FIG. 2B portrays the die's configuration between heating and cooling, and FIG. 2C depicts the die's configuration during cooling. This repeated bending due to extreme temperature cycling and power cycling can cause the die to crack or delaminate. The die either becomes immediately non-functional or its life is shortened. In either event, the die's bending causes undesirable damage.